1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device having a memory device and a logic device formed together on a single chip. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
With reference to FIG. 26, conventionally, a logic device and a memory device are formed on separate chips, which are then placed on a single board. Thus forming a memory device and a logic device on separate chips makes it difficult to maintain high speed characteristic. Accordingly, a so-called eRAM (embedded Random Access Memory), a device having a memory device and a logic device both formed on one chip has been proposed.
In such an eRAM device, the essential subject is to enhance the driving ability of a transistor for a logic device. The driving ability of a transistor can be most effectively enhanced by making a gate oxide film of a transistor thinner. On the other hand, in a memory device, particularly in a DRAM device, thinner a gate oxide film causes a problem specific to DRAM (that is, it does not work unless rising voltage level is increased because of high power supply voltage). Therefore, there is a limitation in making the gate oxide films of both transistors thinner at the same time.
Then, respective gate oxide films for a memory device and a logic device can be formed separately. A possible conventional method of forming gate oxide films separately will now be described with reference to the drawings.
With reference to FIG. 28, a silicon substrate 1 is prepared.
In the case of a device having a DRAM device and a logic device both formed on a chip, there are five types of transistors formed in portions A, B, C, D and E. A logic type NMOS transistor is formed in A, a logic type PMOS transistor in B, a DRAM cell transistor in C, a DRAM array type NMOS transistor in D and a DRAM array type PMOS transistor in E. In FIG. 28, Z represents a boundary portion in an eRAM device, that is, a boundary portion between a memory device and a logic device.
With reference to FIG. 29, an isolation oxide film 2 is formed in the main surface of silicon substrate 1 using LOCOS (Local Oxidation of Silicon method). Next, a gate oxide film 3 is formed after forming a well (not shown) as needed.
With reference to FIG. 30, a resist pattern 4 is formed on the portion other than the portion to have a thinner gate oxide film (in other words, on a portion corresponding to logic types transistors A and B requiring driving ability).
With reference to FIGS. 30 and 31, gate oxide film 3 in portions A and B is removed using resist pattern 4 as a mask to expose surface 11 of a silicon substrate. Resist pattern 4 is then removed.
With reference to FIG. 32, the surface of silicon substrate 1 is oxidized and an usual gate oxide film is formed again. At this time, the thickness of a gate oxide film 31 is larger than that of a gate oxide film 32. That is, the thickness of gate oxide film 32 in portions for transistors A and B is different from that of gate oxide film 31 for transistors C, D and E. Namely, gate oxide film 32 in portions for transistors A and B requiring driving ability is thinner than gate oxide film 31 for transistors C, D and E.
With reference to FIG. 33, a gate electrode film 5 of a transistor is formed on the entire surface of silicon substrate 1.
With reference to FIG. 34, an oxide film 6 is formed on gate electrode film 5.
With reference to FIG. 35, resist patterns 131 and 132 are formed in the portions to form gate electrodes.
With reference to FIGS. 35 and 36, oxide film 6 is etched using resist patterns 131 and 132 as masks. Subsequently, resist patterns 131 and 132 are removed.
With reference to FIG. 36, gate electrode 5 is selectively etched to form gate electrodes 511 and 811 using the resulting patterns 611 and 911 formed of the oxide films as masks.
With reference to FIG. 37, an interlayer insulation film 14 is formed on the entire surface of silicon substrate 1. The formation of contact holes and interconnection layers 15 in interlayer insulation film 14 completes an eRAM.
The foregoing is a possible method of forming gate oxide films separately. This method, however, has a following disadvantage.
With reference to FIG. 30, resist pattern 4 is directly formed on gate oxide film 31, and therefore, gate oxide film 31 contacts with various kinds of impurities (especially metal impurities) contained in resist pattern 4. As a result, the metal impurities can be injected into gate oxide film 31, thereby adversely affecting the reliability of gate oxide film 31.